1. Field of the Invention
The present invention relates to a control method of a multi-channel digital-to-analog (D/A) converting circuit.
The invention is particularly concerned with a control method of a multi-channel digital-to-analog converting circuit for switchingly converting mutiple channel signals with a single D/A converter at no sacrifice of a high repetition rate operation and enabling the reduction of an operation time of a CPU (central processing unit) employed for the switching operation.
2. Description of the Prior Art
FIG. 1A illustrates a circuit diagram of a multi-channel digital-to-analog converting circuit of the prior art. Reference numeral 21 indicates an interface circuit (I/O) to interface a CPU (central processing unit) 26 to each of analog switch groups 24A to 24D. Interface circuits 22A to 22D interface bus signals 32A to 32D connected with the CPU 26 to each of D/A converters 23A to 23D. Each of D/A converters 23A to 23D converts each of bus signals 32A to 32D applied through each of interface circuits 22A to 22D to each of analog signals 33A to 33D.
Analog switch groups 24A to 24D consist of eight analog switches SA.sub.1 to SA.sub.8, SB.sub.1 to SB.sub.8, SC.sub.1 to SC.sub.8 and SD.sub.1 to SD.sub.8, respectively, for time-divisionally transmitting analog signals 33A to 33D delivered from D/A converters 23A to 23D. Reference numerals 25A.sub.1 to 25A.sub.8, 25B.sub.1 to 25B.sub.8, 25C.sub.1 to 25C.sub.8 and 25D.sub.1 to 25D.sub.8 are analog voltage storing circuits for momentarily storing analog signals 34A.sub.1 to 34A.sub.8, 34B.sub.1 to 34B.sub.8, 34C.sub.1 to 34C.sub.8 and 34D.sub.1 to 34D.sub.8 which are respectively applied through analog switches SA.sub.1 to SA.sub.8, SB.sub.1 to SB.sub.8, SC.sub.1 to SC.sub.8 and SD.sub.1 to SD.sub.8.
The CPU 26 sends an analog switch control signal 31 to each of analog switch groups 24A to 24D, respectively, through the interface circuit 21 and bus signal 32A to 32D as digital signals to each of D/A converters 23A to 23D through each of interface circuits 22A to 22D and instructs a ROM (read-only memory) 27 to read the instruction data and a RAM (random access memory) 28 to write and read the data.
An operational principle of the circuit will be described below. Stored data are read as bus signals 32A to 32D from the RAM 28 upon receiving instructions, which are read from the ROM 27, and the signals 32A to 32D are applied to each of D/A converters 23A to 23D through each of interface circuits 22A to 22D.
Each of analog signals 33A to 33D, which are converted to analog by each of D/A converters 23A to 23D, is time-divisionally delivered from each of analog switches SA.sub.1 to SA.sub.8, SB.sub.1 to SB.sub.8, SC.sub.1 to SC.sub.8 and SD.sub.1 to SD.sub.8 forming each of analog switch groups 24A to 24D which are switched on or off by receiving the analog switch control signal 31 from the CPU 26 through the interface circuit 21.
Each of analog voltages 34A.sub.1 to 34A.sub.8, 34B.sub.1 to 34B.sub.8, 34C.sub.1 to 34C.sub.8 and 34D.sub.1 to 34D.sub.8, which is time-divisionally obtained through each of analog switches to SA.sub.1 to SA.sub.8, SB.sub.1 to SB.sub.8, SC.sub.1 to SC.sub.8 and SD.sub.1 to SD.sub.8, is momentarily stored by each of analog voltage storing circuits 25A.sub.1 to 25A.sub.8, 25B.sub.1 to 25B.sub.8, 25C.sub.1 to 25C.sub.8 and 25D.sub.1 to 25D.sub.8. As an analog voltage storing circuit 25A, etc., a circuit shown in FIG. 1B can be employed which comprises an analog voltage storing capacitor 29 and a high input impedance operational amplifier 30.
The above-described operation of four channels, which comprise four D/A converters 23A to 23D, is respectively executed in parallel as shown in a time chart of FIG. 1C.
Referring to FIG. 1C, each of groups of analog switches SA.sub.1 to SA.sub.8, SB.sub.1 to SB.sub.8, SC.sub.1 to SC.sub.8 and SD.sub.1 to SD.sub.8 switches synchronously with each other and each analog voltage storing capacitor 29 (FIG. 1B) is charged an analog voltage every repetition of charging cycle times. Thus, the charging operation of each capacitor 29 in four channels in parallel makes the processing time of CPU 26 (FIG. 1A) rather reduced and allows CPU 26 to have long blank time Tc available for other operations than switching.
Another circuit diagram of the prior art is shown in FIG. 2A, wherein like reference numerals and symbols represent like elements which correspond to those in FIG. 1A.
The circuit diagram shown in FIG. 2A differs from that shown in FIG. 1A in the point that a single D/A converter 23 converts a bus signal 32 through an interface circuit 22 to analog to obtain an analog output 33 which is distributed to each of analog switch groups 24A to 24D.
As shown in FIG. 2B, illustrates an operational timing of this circuit, analog switches SA.sub.1 to SA.sub.8 of one analog switch group 24A are switched on at first and each analog voltage storing capacitor 29 (FIG. 1B) is charged during every charging cycle time. After that, other analog switches SB.sub.1 to SB.sub.8 are switched on and each analog voltage storing capacitor 29 is charged alike. Thus, analog switches SA.sub.1 to SA.sub.8, SB.sub.1 to SB.sub.8, SC.sub.1 to SC.sub.8 and SD.sub.1 to SD.sub.8 are switched successively and the like operation continues repeating.
A time required for switching each of analog switches SA.sub.1 to SA.sub.8, SB.sub.1 to SB.sub.8) SC.sub.1 to SC.sub.8 and SD.sub.1 to SD.sub.8 is e.g. 1 ms as shown in FIG. 2B and the charging cycle time of the analog voltage storing capacitor 26 is 4 ms+Tc (blank time), resulting in little blank time Tc for the CPU.
A circuit diagram of the prior art shown in FIG. 1A provides a relatively high repetition rate operation, leaving long blank time Tc available for other operations of CPU 26 than switching because each analog voltage storing capacitor 29 is charged in each of four channels in parallel. However, the circuit comprising four sets of D/A converters and interface circuits is expensive in cost.
Another circuit of the prior art shown in FIG. 2A is simple and not expensive because only a singal set of a D/A converter and an interface circuit is employed. However, switching operation of each of analog switches under the software control of a CPU 26 requires the CPU 26 occupied for a long time with not enough blank time available for other operations of the CPU 26 then switching because of a long analog voltage charging cycle time as shown in FIG. 2B. Another CPU is therefore required for other operations.